Low Power Reduced Router Noc Architecture Design with Classical Bus Based System

Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing communication requirements in digital systems. Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many-core systems. A novel switching mechanism, called virtual circuit switching, is implemented with circuit switching and packet switching. A path allocation algorithm is used to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized. The experimental results show that the hybrid scheme can efficiently reduce the communication latency and power. VCS connections and CS connections can be limited to the class of communications that need guaranteed latency, and packet switching can be used to serve the best effort traffic. To overcome this classical bus based system for NOC is proposed to reduce the number of switches and network interfaces to yield better latency and power consumption. Key Words-Network-on-chip (NOC), Virtual circuit-switched (VCS) Connections, Classical bus based system.